1. Field of the Invention
The present invention relates to clock signal generation. More specifically, the present invention relates to a state machine based phase-lock-loop generator of clock signals for a Universal Serial Bus (USB) protocol.
2. Description of the Prior Art
A Universal Serial Bus is a high-speed serial bus for communicating between a host computer and one or more USB devices, or more recently between two USB devices. The host and each USB device comprise a Serial Interface Engine (SIE) to provide an interface between the devices and to handle low-level USB functions such as error checking, hand-shaking, and token generation.
The SIE must generate transmit and receive clock signals to insure synchronization between the devices. Obviously for two-way communication between the devices, each device must include both a transmit clock and a receive clock. The transmit clock signal has a regular duty cycle and normally operates at 12 MHz or at 1.5 Mhz for slow devices. The receive clock cycle may be stretched or shrunk to accommodate data jitter in the USB and still latch on to the transmitting clock""s signal as discussed in the USB specification.
One conventional clock scheme uses an analog phase-lock-loop (APLL) device. This method can introduce process dependencies, reduces re-usability, and has generally been replaced by digital state machines.
Early attempts at using a digital phase-lock-loop (DPLL) state machine required separate transmit and receive clocks and an outside circuit to select the appropriate clock. In an effort to eliminate possible malfunctioning of the selecting circuit and the difficulties with designing and maintaining a selecting circuit, U.S. Pat. No. 6,088,811 discloses a DPLL state machine replacing the selecting circuit with an intermediate state and is hereby included by reference. The intermediate state forms a bridge between two distinct groups of states (one for transmitting and one for receiving) and allows alternation between the two modes (groups of states) as appropriate to form a single DPLL state machine.
While the above-described disclosure does represent an improvement over the previous prior art, it still requires a complex design of two separate groups of states, an intermediate state, and complex circuitry to avoid entering undefined states.
It is therefore an objective of the claimed invention to provide a single mode state machine that uses a single group of states to simplify the complex circuitry in a state machine based phase-lock-loop (PLL) scheme for recovering the Universal Serial Bus (USB) clock from the USB.
The claimed state machine running at 4X speed includes only five states and generates a 1X speed clock. When transmitting, the claimed invention acts as a divide-by-four counter and divides the 4X clock into a 1X clock to be used by control logic (for example, a Serial Interface Engine). When receiving, the same state group acts as a divide-by-four counter with the received data""s status being continuously monitored to dynamically adjust the duty cycle of the receiving clock.
The claimed invention changes from one state to another along predefined paths.
The exact selection of path is determined by the logical AND of a phase change within the data and a signal indicating whether the state machine is currently transmitting or receiving.
It is an advantage of the claimed invention that a single mode clock with a single group of 5 states is used for both transmitting and receiving USB signals. The claimed invention uses a single group of states to simplify design and reduce circuitry complexity, manufacturing costs, and power consumption in a PLL scheme to recover the Universal Serial Bus (USB) clock from the USB. The small size of the state machine facilitates implementation in only three bit registers.